1. Field of the Invention
The present invention generally relates to a method and apparatus for analyzing a delay defect which analyze a delay defect in an integrated circuit, and more particularly, to a method and apparatus for analyzing a delay defect which enable rapid and unique determination of a circuit portion that is a bottleneck in frequency performance.
2. Description of the Related Art
With gradual increase in the frequency of an operational clock pulse fed to an LSI, the LSI becomes non-operative. In this situation, if a circuit portion that limits the frequency is found, the cause that makes the LSI non-operative can be determined.
By determining the cause and modifying the problematic unit eventually, design for higher performance as well as for higher frequency yield rate can be achieved.
Additionally, when manufactured LSIs are shipped, it is required to perform inspection on whether or not the LSIs have the specified frequency performance.
Based on the foregoing background, the frequency performances of manufactured LSIs are tested.
The scan test method is among the test methods. The scan test method, as illustrated in FIG. 8, provides a path (scan chain) to control and observe all the flip-flops in an LSI from external pins directly, sets respective test patterns for the flip-flop in the LSI by using the scan chain, observes how the LSI operates in response to the test patterns, and tests whether or not the manufactured LSI has desired performances (such as logic performance and frequency performance).
In a conventional technique, in order to determine, according to the scan test method, which circuit portion of an LSI is a bottleneck in frequency performance, a test pattern (which realizes a slow-to-rise delay defect), which changes the values at the input or the output pin of each logic element in the LSI from 0 to 1, and a test pattern (which realizes a slow-to-fall delay defect), which changes the values at the input or the output pin of each logic element in the LSI from 1 to 0, are created. Then, it is found out which circuit portion of the LSI is a bottleneck in frequency performance by using the test patterns.
In other words, as illustrated in FIG. 9, when a slow-to-rise delay defect is given to the output pin of a logic element located between a transmission latch and a reception latch, by using the test pattern and through the transmission latch, the value at the output pin of the logic element is made to change from 0 to 1 according to the first pulse, and then, through the reception latch, it is ascertained whether or not the value at the output pin of the logic element has changed from 0 to 1 according to the second pulse set based on the pulse period of a testing frequency, whereby it is ascertained whether or not a slow-to-rise delay defect is being caused in the logic element.
However, in the conventional technique, a slow-to-rise delay defect or a slow-to-fall delay defect is given to the input or the output pin of each logic element in an LSI. Therefore, it is required to create a great number of test patterns, whereby it is difficult to determine the circuit portion that is a bottleneck in frequency performance rapidly.
Here, with regard to a delay test in which a slow-to-rise delay defect and a slow-to-fall delay defect are detected, the segment delay test is known that is disclosed in Non-Patent Document 1 (K. Heragu, J. H. Patel, et al, “Segment Delay Faults: A New Fault Model”, Proc. VLSI Test Symposium, 1996).
Meanwhile, in a high-reliability LSI, a great number of checking circuits, such as a parity-error checking circuit and the like, are integrated. Furthermore, in order to make it possible to determine in which portion in an LSI a parity error or the like is caused, identifiers named “region codes (RCs)” are given to the checking circuits.
With gradual increase in the frequency of an operational clock pulse fed to an LSI, the LSI becomes non-operative. However, in case the parity-error checking circuits are integrated, a parity error is caused and the region code to which a checking circuit that has detected the parity error belongs can be obtained.
It is possible to estimate which circuit portion is a bottleneck in frequency performance according to the region code obtained as described above.
Here, Patent Documents 1 to 3 described below disclose techniques related to the present invention.
Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-214732) discloses an invention in which, in order to facilitate the delay defect analysis, a hardware circuit is added.
However, the present invention does not employ any configuration in which, for performing the delay defect analysis, a hardware circuit is added.
Additionally, Patent Document 2 (Japanese Patent No. 3605506) discloses an invention detecting the period T1 of an operational clock pulse with which the LSI does not operate normally and the period T2 of an operational clock pulse with which the LSI operates normally. Then the invention sets the period of an arbitrary pulse among n operational clock pulses to T2 and sets the periods of the other operational clock pulses to T1. N denotes the number of operational clock pulses in the duration from the moment when predetermined data is inputted to an LSI to the moment when the data that responds to the input data is outputted. Then, the invention searches the critical path by checking the position of the operational clock pulses the period of which is set to T2 among n operational clock pulses when normal data is outputted.
However, the present invention employs a configuration in which a delay-defect position of an LSI is determined by using test patterns. Therefore, the configuration of the present invention is completely different from that of the invention disclosed in Patent Document 2.
Additionally, Patent Document 3 (Japanese Patent No. 3450814) discloses an invention related to optimal pipelining control in which the critical path is taken into consideration.
As described above, in the conventional technique, a test pattern, which changes the values at the input or the output pin of each logic element in the LSI from 0 to 1, and a test pattern, which changes the values at the input or the output pin of each logic element in the LSI from 1 to 0, are created, and by using the test patterns, it is found out which circuit portion in the LSI is a bottleneck in frequency performance.
However, in the foregoing conventional technique, a slow-to-rise delay defect or a slow-to-fall delay defect is given to the input or the output pin of each logic element in an LSI. Therefore, it is required to create a great number of test patterns, whereby it is difficult to determine the circuit portion that is a bottleneck in frequency performance rapidly.
Meanwhile, a region code to which a check circuit, detecting a parity error caused with gradual increase in the frequency of an operational clock pulse fed to an LSI belongs can be used to estimate which circuit portion is a bottleneck in frequency performance.
However, a circuit that is covered by a single region code includes several tens to several hundreds of latches (flip-flops) as memory devices.
Therefore, with a method in which a circuit portion that is a bottleneck in frequency performance is estimated by using region codes, it is difficult to determine the circuit portion that is a bottleneck in frequency performance uniquely.